Scan-based testing, as described in as described by Eichelberg in U.S. Pat. No. 3,784,907, and Zasio et al. in U.S. Pat. No. 4,495,629, has been the staple of Design for Testability methodology for over 30 years. The technique drives its strength from its ability to replace the state variables (i.e. flip-flops) that make up a sequential circuit by pseudo inputs and outputs whose values can be set arbitrarily or be observed by connecting the memory elements in a serial shift register configuration. Since serial shift (i.e. scan) actions can be employed to set the flip-flops of the Circuit Under Test (CUT) to any arbitrary set of values, the process transforms a sequential circuit into a virtual combinational circuit where Scan_In and Scan_Out activities are defined as macro operations to set (i.e. control) and observe the state variables of the CUT. Using this methodology, Scan_In is performed to apply the inputs at the pseudo-input pins of the CUT, followed by a Capture operation, which captures the response of the CUT to the input values. Next, Scan_Out is employed to read out the captured results at the memory elements that are used to implement the state variables. Furthermore, Scan_Out of the captured test results for a previous test can be overlapped with the Scan_In of the input values for the next test in order to reduce some of the time overhead of scan-based testing.
As scan technology has enabled transforming the problem of sequential test pattern generation into the much easier problem of test pattern generation for a combinational circuit it has led to the development of very efficient combinational ATPG algorithms. However, with increasing circuit complexity, which is often measured in terms of the number of state variables (i.e. flip-flops or latches used to implement it) the total number of serial bits that have to be scanned in and out in serial fashion has become a problem. To combat this problem, designers have reverted to implementing parallel scan whereby the overall scan chain is broken into a number of independently operable serial scan chains so that the effective serial scan overhead can be reduced by a factor that is equal to the number of parallel scan chains. For example, a 100,000-bit serial scan chain may be implemented as 10, independently operable scan chains of 10,000 bits each and thereby reduce the total number of shift cycles necessary to load/unload all of the 100,000 bits by a factor of 10.
Parallel scan can help alleviate some of the serial scan, but test time issues limit its effectiveness to the number of independently operable scan chains that can be implemented on a target Integrated Circuit (IC). Each independent scan chain requires a pair of Scan_In/Scan_Out pins that are directly accessible using the primary I/O pins of the IC. Most IC's are limited by the number of their I/O pins that are available for scan and other test purposes. Parallel scan can be implemented using a sharing of some of the primary I/O pins between their functional and Scan roles. Unfortunately, shared I/O pins impact the target IC's maximum operating speed. Furthermore, it is not possible to take advantage of parallel scan unless the Automatic Test Equipment (ATE) that will be used to test the target IC has the ability to feed and observe data on the parallel scan channels simultaneously. As might be expected, often the ATE imposed limit on the independently operable scan chains is more severe than the limit imposed by the target IC designer. In addition to its limitations as described above, parallel scan, does not address a crucial issue. Whether a single, serial scan or an n-channel parallel scan architecture is used, the total number of bits of data that need to be scanned-in and scanned-out for each ATPG vector remains the same. Today, it is not unreasonable to expect a complex IC to contain close to IM flip-flops that are scanable. Considering that for each ATPG vector we may need an input vector, an (expected) output vector, and (possibly) a mask vector to indicate whether an output bit value may be used reliably, 2K×1 M×3/8=750 MB of high-speed ATE memory may be required to hold all of the test patterns and the expected results. The total volume of test related data and the need for increased physical bandwidth (i.e. number of externally controllable parallel scan chains) are fast becoming dominant factors in determining overall test cost of complex ICs. The concerns described above have made it desirable to reduce the total data volume needed for scan-based ATPG. To this end, a crucial observation has been made that for any given ATPG vector only a very small percentage of the total number of scanable bits are needed to be set to deterministic values; the vast majority of the scanable bits are free and can be (are) set to pseudorandom values to achieve additional incidental fault coverage. The ATPG program sets these bits to logic 1 or logic 0 values, but their specific values are not critical and another set of pseudo random values may also be employed without any appreciable change in fault coverage. This observation has led to the development of techniques that focus on data compression of the scan vectors whereby the pre-determined bit values are preserved while the pseudo random values can be filled in a manner to achieve greater data compression. For example, U.S. Pat. No. 6,327,687, by Raj ski et al. describes such a technique.
The primary goal in test data compression for scan-based testing using ATPG vectors is to store sufficient information off the chip (i.e. on the ATE) that allows setting pre-determined bit positions of each scan vector to their ATPG-determined values while setting the remaining bit positions to values that aid in maximum data compression. Characteristic of all state-of-art techniques to achieve this is that they achieve their objective while length (i.e. number of clock cycles) for the scan operations remains unchanged before and after test data compression. This has been deemed necessary since scan in of input values for the present test vector is overlapped with scan out of test results from the previous test vector such that the two lengths need to be equal; Extending this requirement over the entire test vector set is achieved by keeping the scan-length be constant over the entire test set. In this case, reduction of scan test data volume can only be achieved by scanning a seed value into a data decompressor network that receives the shorter-length seed values in order to produce the actual values to be fed into the scan chains. Typically, the decompressor network is based on an LFSR which is implemented inside the target device under test (DUT) and a set of simultaneous EXOR-equations need to be solved to determine the seed values to be fed into the LFSR circuit during test.
A recent U.S. patent application Ser. No. 10/351,276, filed Jan. 24, 2003, describes a different approach that is based on a technique whereby the hereto unquestioned overlapping of the scan-in and scan-out operations is considered separately from each other. One aspect of the new technique is driven by the observation that, even after compaction, only a very a small percentage (less than 2%) of bit values of each ATPG-generated scan-test vectors are set to pre-determined values (called Care_In values) while the remaining bits are set to pseudorandom values with hopes of achieving increased incidental coverage. In similar fashion, Care_Out positions are defined as bit positions along a scan-chain that contain pre-determined test results that are indicative of the pass/fail nature of tests executed by previous test vector. Similar to the small number of Care_In positions for each test vector, there are only a small percentage of Care_Out positions for each given result vector. Separation of the scan in and scan out operations from each other enables using this fact in reformulating the scan in problem as:
Given the present-state of values along a scan chain, find an efficient way to set all Care_In positions to pre-determined values without concern about values achieved in other, non-Care_In bit positions. Similarly, the scan out problem can be reformulated as:                Given the set of test results along a scan chain, find a cost-efficient structure to observe all of the Care_Out values, either directly or using a MISR.        
As with the previous U.S. patent application Ser. No. 10/351,276, filed Jan. 24, 2003, a unique advantage of the present invention is, the separation of Scan_In and Scan_Out problems from one another, which leads to a very effective solution to the problem of reducing data volume and test time for scan-based testing of IC's. The present invention extends the previous Application, with improved methods for computing such compressed test vectors and with improved circuitry that eases its implementation in hardware.
While reading the remainder of the descriptions, it is useful to focus on number of cycles for the Scan_In and Scan_Out operations, in the remainder of this patent, the inventors are using this terminology as a semaphore for the volume of test-related data since, for a given number of externally accessible Scan_In/Scan_Out ports, a smaller number of scan cycles implies less data volume.